In many semiconductor (SC) devices and integrated circuits (ICs), capacitive coupling from the control element or electrode to the output region of the device limits the device performance. Well known examples are trench type field effect transistors (Trench-FETS), V-type metal-oxide-semiconductor (VMOS) transistors, T-type metal-oxide-semiconductor (TMOS) transistors, lateral diffused metal-oxide-semiconductor (LDMOS) or other metal-oxide-semiconductor field effect transistors (MOSFETs) implemented in power IC platforms, where the capacitance Cgd between the control gate and the drain region of the device is larger than desired. This excess gate-drain capacitance Cgd can significantly degrade overall device and IC performance. It will be understood by those of skill in the art that the designations “metal-oxide-semiconductor” and the abbreviation “MOS” and “MOSFET” as used herein include devices utilizing any kind of dielectric not just oxides and any kind of conductor not just metals.
FIG. 1 is a simplified schematic cross-sectional view of generalized vertical power semiconductor device 20 according to the prior art, illustrating how the gate-drain capacitance Cgd can arise. For convenience of explanation, it is assumed in connection with device 20 and other devices illustrated herein that such devices are N-channel power devices formed in silicon semiconductor (SC) material, but this is not intended to be limiting and persons of skill in the art will understand that other semiconductor (SC) materials may be used, that other substrates may be used (e.g., SC on insulator), and that P-channel devices and other kinds of both power and small signal devices can be formed by appropriate interchange or rearrangement of the various doped regions. Device 20 has semiconductor substrate 21, with upper surface 22 and lower surface 23, in which are formed source region 24 of a first conductivity type (e.g., N+), body region 25 of a second, opposite conductivity type (e.g., P BODY), drift space or region 26 of the first conductivity type (e.g., N DRIFT SPACE) and drain region 27 of the first conductivity type (e.g., N+DRAIN). Cavity 28 is formed in SC substrate 21 extending from upper surface 22 through source region 24 and body region 25 to or into drift region or space 26. Gate dielectric 29 separates P BODY region 25 (and also N DRIFT SPACE 26) from gate 30 located within cavity 28. Gate 30 is conveniently of polycrystalline semiconductor (e.g., POLY GATE) of, for example silicon, but any conductor may be used. Gate dielectric 29 is conveniently of silicon oxide although other insulating materials may also be used. Gate contact 32 with terminal 33 is formed in ohmic contact with POLY GATE 30. Source contact 34 with terminal 35 is formed in ohmic contact with source region 24. Dielectric lateral spacer 36 is conveniently provided to separate gate and source contacts 32, 34. Drain contact 38 with terminal 39 is provided in ohmic contact with drain region 27. When device 20 is appropriately biased, electron current Isd flows from source region 24 to drain region 27, under the control of gate 30. Gate-drain capacitance 37, abbreviated as Cgd, couples gate 30 and drain region 27 across gate dielectric 29 through N DRIFT space or region 26.
Various attempts have been made in the prior art to reduce Cgd by, for example, making cavity 28 “V” shaped and/or by providing region 39 of lower dielectric constant material between bottom 31 of gate 30 and N DRIFT space or region 26 and drain 27. However, none of these and other approaches have been successful in minimizing Cgd since, for example, the lower dielectric constant materials that might be used in region 39 still have dielectric constants k significantly larger than vacuum or air. Accordingly, there is an ongoing need to provide improved fabrication methods and structures for semiconductor devices and ICs capable of achieving lower Cgd than has hitherto been possible, and that are compatible with established semiconductor device and IC fabrication methods and materials.